Design structure for improved current controlled oscillation device and method having wide frequency range

ABSTRACT

A design structure embodied in a machine readable medium used in a design process includes a current controlled, phase locked loop device having a phase detector configured to compare a reference frequency to an output frequency of a current controlled oscillator (ICO), a charge pump coupled to the phase detector and a low pass filter coupled to the charge pump. A voltage to current (V to I) converter is coupled to the low pass filter, providing an output current for integral control of the ICO. A control circuit is coupled to the ICO, and receives increment and decrement outputs of the phase detector, wherein the control circuit is configured to provide proportional control of the ICO through an amount of bias current applied thereto.

This non-provisional U.S. Patent Application is a continuation-in-partof U.S. patent application Ser. No. 11/278,196, which was filed Mar. 31,2006, now U.S. Pat. No. 7,355,486, and is assigned to the presentassignee.

BACKGROUND

The present invention relates generally to current controlledoscillation (ICO) devices, and, more particularly, to a design structurefor an improved ICO device having wide frequency range and integratedproportional frequency control capable of operation at low supplyvoltages.

Controlled oscillators are used in a variety of integrated circuits forapplications such as, for example, signal generation and detection, aswell as in phase locked loop (PLL) circuits. In a controlled oscillator,the frequency of an output signal is responsive to a control signalprovided thereto. There are various types of controlled oscillators,with one of the more common types being a current controlled oscillator(ICO). A typical ICO includes a controlled current source coupled to aring oscillator, which in turn features a chain of inverter stages(typically an odd number). The output of one inverter in the stage iscoupled to the input of a succeeding inverter, and so on, with theoutput of the last inverter fed back to the input of the first inverterin the stage. Typical inverters are formed from CMOS transistors,although other types of devices may also be used.

The frequency of the output signal of an ICO is inversely proportionalto the delay/switching time of the inverters that form the oscillator.In turn, the switching time of an inverter corresponds to the timeneeded to charge and discharge the input capacitance of a successiveinverter to a level respectively above or below the switching thresholdof the successive inverter. The charge and discharge period isdetermined by the magnitude of current that is used to charge the inputcapacitance. It is this charging current that is provided and controlledby the controlled current source.

One disadvantage associated with conventional current controlledoscillators is that the gain of the oscillator is not controllable at agiven operating frequency. This is particularly the case for anoscillator that is used over a wide range of operating frequencies, asthe gain of a conventional ICO (i.e., the relationship of outputfrequency versus bias current) is constrained by the desired frequencyrange. It would therefore be desirable to be able to configure a widerange oscillator for applications such as phase locked loops, forexample, that also keeps the gain at a low level so that the overallloop bandwidth can be optimized.

SUMMARY

The foregoing discussed drawbacks and deficiencies of the prior art areovercome or alleviated by a design structure embodied in a machinereadable medium used in a design process, the design structure includinga current controlled, phase locked loop device including a phasedetector configured to compare a reference frequency to an outputfrequency of a current controlled oscillator (ICO), a charge pumpcoupled to the phase detector and a low pass filter coupled to thecharge pump. A voltage to current (V to I) converter is coupled to thelow pass filter, providing an output current for integral control of theICO. A control circuit is coupled to the ICO, and receives increment anddecrement outputs of the phase detector, wherein the control circuit isconfigured to provide proportional control of the ICO through an amountof bias current applied thereto.

BRIEF DESCRIPTION OF THE DRAWINGS

Referring to the exemplary drawings wherein like elements are numberedalike in the several Figures:

FIG. 1 is a schematic block diagram of a phase locked loop employing aconventionally configured current controlled oscillator;

FIG. 2 is a schematic block diagram of a phase locked loop employing acurrent controlled oscillator configured in accordance with anembodiment of the invention;

FIG. 3 is a more detailed block diagram of the control circuit andcurrent controlled oscillator of FIG. 2;

FIG. 4 is a schematic diagram illustrating an exemplary delay stage usedin the current controlled oscillator of FIGS. 2 and 3;

FIG. 5 is a detailed schematic diagram of the control circuit of FIGS. 2and 3;

FIG. 6 is a graph illustrating bias current versus frequency curves forthe current controlled oscillator, as a function of the adjustable gainof the delay stages, in accordance with a further embodiment of theinvention; and

FIG. 7 is a flow diagram of an exemplary design process used insemiconductor design, manufacturing, and/or test.

DETAILED DESCRIPTION

Disclosed herein is a novel design structure embodied in a machinereadable medium used in a design process, which provides currentcontrolled oscillator that reduces jitter in a PLL by providing thecapability of changing the gain of the ICO curves, depending upon thefrequency of operation. By reducing the gain of the ICO, the PLL loopbandwidth can be shaped to reduce the overall jitter of the system. Inaddition, a novel control circuit provides both proportional andintegral control for the ICO, which allows for the ICO to operate at lowsupply voltages.

Referring initially to FIG. 1, there is shown a schematic diagram of aphased locked loop 100 utilizing a conventional current controlledoscillator. As is shown, the PLL 100 includes a phase detector 102,charge pump 104, low pass filter 106 (with at least one resistor elementand one or more capacitor elements), voltage to current converter 108,and a current controlled oscillator 110 and output buffer 112 placed ina negative feedback configuration. There may also be a divide-by-Ncounter 114 included in the feedback path in order to obtain fractionalmultiples of the reference frequency F_(ref) out of the PLL 100.

The ICO 110 generates a periodic output signal F_(out) that is comparedto the reference frequency F_(ref). If the output signal F_(out), forexample, begins to fall behind the reference frequency, then the phasedetector 102 causes the charge pump 104 (through output signal “INC”) tochange the control voltage (converted to control current) to speed upthe ICO 110. Conversely, if the output signal begins to creep ahead ofthe reference signal, than the phase detector 102 causes the charge pump104 (through output signal “DEC”) to change the control current to slowdown the ICO 110. The low pass filter 106 provides both proportional andintegral control of the ICO 110, and smoothes out any abrupt controlinputs from the charge pump 104.

As indicated previously, ICOs (such as those built on microprocessorchips), being formed from a ring of active delay stages, suffer frommore jitter than other types of oscillators as a result of the fixedgain thereof over a given range of operating frequencies and theconsequent inability to shape the loop bandwidth.

Therefore, in accordance with an embodiment of the invention, FIG. 2illustrates a schematic block diagram of a phase locked loop 200employing a novel current controlled oscillator 210 and associatedcontrol circuit 216, featuring a wide frequency range, integrated andproportional control, and wherein the gain may be adjustably decreasedat a given operating frequency in order to provide improved noiseperformance at low operating voltages. For ease of description, similarcomponents of a phased locked loop are designated with the samereference numerals as shown in FIG. 1.

It will first be noted that the control circuit 216 providesproportional frequency control for the ICO 216 by receiving the INC andDEC outputs from the phase detector 102. The INC and DEC pulses arecompared within the control circuit 216, and determine the amount ofbias current provided to the ICO 210, which in turn determines thefrequency of operation thereof. As such, the low-pass filter 206 needonly provide a capacitive element for integral frequency control, thevoltage of which is again converted to a current through V to Iconverter 108. As described in further detail hereinafter, the output ofthe V to I converter 108 is used by the control circuit 216 and thus theICO 210.

A bias generator 218 provides a pair of reference current signals foruse by the control circuit 216 in determining control voltages appliedto the ICO delay elements, that in turn control the bias current of theICO 210 and hence the frequency thereof. In addition, a gain controlblock 220 provides a control signal applied directly to delay elementsof the ICO 210 so as to adjustably control the amount of gain of theelements and thereby select the gain of the ICO 210. The operation ofthe gain control feature is also described in further detailhereinafter.

Referring now to FIG. 3, a more detailed block diagram of the dashedportion of FIG. 2 is illustrated. In particular, the ICO 210 includes(in an exemplary embodiment) a two-stage, latch-based configuration.Because both delay stages 302 a, 302 b utilize differential inputs andoutputs (i.e., the logical true and complement signals of the latch), anodd number of stages is not needed. In addition to the power rail inputs(V_(DD), V_(SS)) each latch delay stage 302 a, 302 b is provided withthe gain control signal VCNTL generated by the gain control block 220 ofFIG. 2. As also shown in FIG. 3, a reset circuit 304 is provided inorder to initially establish complementary input voltages to the inputterminals VIN_P, VIN_N, of the second delay stage 302 b and facilitatethe oscillating output of the ICO 210.

The inputs and outputs of the control circuit 216 are also labeled inFIG. 3. The inputs include the INC signal and DEC signal from the phasedetector 102 of FIG. 2, as well as the two reference signals IPUMP_REF1,IPUMP_REF2, generated by the bias generator 218. The output current fromthe V to I converter 108 is input into the control circuit 216, the nodevoltage of which (NBIAS) represents one of the two bias voltages for thedelay stages 302 a, 302 b, that in turn control the bias currentthereof. The other bias voltage (PBIAS) is an output of the controlcircuit 216, which is described in additional detail later.

FIG. 4 is a schematic diagram illustrating an exemplary delay stage 302used in the current controlled oscillator 210 of FIGS. 2 and 3. As isshown, the stage 302 includes biasing transistors P1 and N1, theconductivity of which determines the amount of current through the celland hence the frequency. A higher cell current leads to a higherfrequency because the cell delay is reduced. The fully differential cellcan thus be used to build ring oscillators of varying lengths. The gateof P1 is coupled to PBIAS, the voltage of which is determined by controlcircuit 216, while the gate of N1 is controlled by the voltage at NBIAS,coupled to the output of the V to I converter 108 as stated above. Thelatch portion of the delay stage 302 includes NFETs N2 and N3, alongwith PFETs P2 and P3. In the embodiment depicted, the input signals tothe stage 302 (VIN_P, VIN_N) are shown coupled to NFETS N2 and N3,respectively, while the PFETs P2 and P3 are cross-coupled. However, theinput signals could alternatively be coupled to P2 and P3 with N2 and N3being cross-coupled.

As will further be noted from FIG. 4, PFETs P2 and P3 are cross-coupledthrough a pair of NFETs N4 and N5. This provides the adjustable gaincontrol of the ICO through a suitable voltage on VCNTL. The higher thebiasing voltage of VCNTL, the more conductive the cross coupling pathsand thus the greater the gain. In a conventionally configured delaylatch, the cross coupling is a direct short circuit, and thus the gainof the cell is maximized and not adjustable. Accordingly, where it isdesired to reduce the gain of the ICO, the value of VCNTL can be loweredso as to increase the resistance of the cross coupling paths.

Referring now to FIG. 5, the control circuit 216 is schematicallyillustrated in further detail. When the output frequency of the ICO isequal to the reference frequency, no changes in the output frequency areneeded. In other words, the output values INC and DEC of the phasedetector are zero. As to the increment portion of the control circuit,it will be seen that so long as INC is zero, PFET P8 will maintain thegate of PFET P9 at the supply rail, thus keeping P9 off. Therefore, theonly current flowing through diode configured NFET N11 is from the V_Icurrent input (generated by V_I converter 108). The voltage at this nodealso represents the output NBIAS voltage used to control the N1 gate ofthe delay stages of FIG. 4. Conversely, the diode connected PFET P10, inseries with NFET N10 determines the output PBIAS voltage used to controlthe P1 gate of the delay stages of FIG. 4.

Thus, it will be seen that the V_I current input provides the integralportion of the control of the ICO. In the event that the phase detector102 (FIG. 1) determines that the output frequency falls behind thereference frequency, then the value of INC changes to high, therebydisabling PFET P8. As a result, the gate of PFET P9 and diode connectedPFET P7 are decoupled from the supply rail. This allows current to flowthrough the current mirror P7 and N9, as determined by IPUMP_REF1 andN6, and consequently through P9. The result is to (proportionally) addto the amount of current provided by V_I, which in turn increases thevalue of NBIAS and decreases the value of PBIAS, thereby providing morebias current to the delay cells and increases the oscillation frequencythereof. Once the output frequency catches up to the referencefrequency, INC will return to low and cause P8 to deactivate P9 andremove the extra current flowing through N11. This returns the ICO backto the integral control thereof, as determined by the value of V_I.

On the other hand, if the output frequency begins to exceed thereference frequency, then the value of DEC changes to high, therebydisabling PFET P6 and decoupling PFET P4 and diode connected PFET P5from the supply rail. Once current begins to flow through P4 and diodeconnected NFET N8 (as determined by IPUMP_REF2), N7 will becomeconductive. Because N7 is connected in parallel with respect to N11 itwill therefore (when rendered conductive) decrease the amount of currentthrough N11 as supplied by V_I. This results in decreasing the voltageat output NBIAS and increasing the voltage at output PBIAS, therebydecreasing the bias current applied to the delay cells and reducing theoutput frequency thereof. Once the output frequency again matches thereference frequency, DEC will return to zero, thus causing the gates ofP4 and P5 to be pulled back up to V_(DD), shutting off current throughN7 and increasing the value of current through N11 to the amountdetermined by integral current control signal V_I. In the exemplaryembodiment depicted, the frequency range of the ICO 210 with a supplyvoltage of about 0.8 V is about 70 MHz to about 1033 MHz, representing afactor of more than 10.

One key advantage of this method of proportional control is that theamount of current added to or subtracted from the V_I current is easy tochange, simply by changing the bias voltage at nodes IPUMP_REF1 andIPUMP_REF2. Changing the current added or subtracted is equivalent tochanging the value of the “R” in the RC low pass filter of FIG. 1. Theloop bandwidth and the damping are affected by the equivalentresistance, and thus this provides an easy way to control both the loopbandwidth and damping.

FIG. 6 is a plot of the output frequency versus the bias current at twodifferent values of the control voltage VCNTL (which again representsthe output of the gain control block 220 of FIG. 2). As can be seen, theeffect of the VCNTL is to flatten the curves such that the gain isreduced. By way of example, at an operating frequency of 300 MHz, thegain is about 4.93 MHz/μA with VCNTL=1.0 V, but only 3.21 MHz/μA withVCNTL=1.5V. Also shown in FIG. 6 is the output frequency vs. biascurrent curve for a conventional delay cell with no gain controlcapability. That is, the NFETs N4 and N5 in FIG. 4 are simply replacedwith short circuits. As will thus be appreciated, the use of the seriesNFETs along with a variable VCNTL voltage affords a means of changingthe slope (i.e., the gain) of the characteristics at any desiredfrequency. The gain of an oscillator impacts the phase noisecharacteristics through the bandwidth of the control loop. Thus, byreducing the bandwidth of the loop, the output noise may also bereduced.

FIG. 7 is a block diagram illustrating an example of a design flow 700.Design flow 700 may vary depending on the type of IC being designed. Forexample, a design flow 700 for building an application specific IC(ASIC) will differ from a design flow 700 for designing a standardcomponent. Design structure 710 is preferably an input to a designprocess 720 and may come from an IP provider, a core developer, or otherdesign company or may be generated by the operator of the design flow,or from other sources. Design structure 710 comprises circuitembodiments 200, 210, 302, 216 in the form of schematics or HDL, ahardware-description language, (e.g., Verilog, VHDL, C, etc.). Designstructure 710 may be contained on one or more machine readablemedium(s). For example, design structure 710 may be a graphicalrepresentation of circuit embodiments 200, 210, 302, 216 illustrated inFIGS. 2-5. Design process 720 synthesizes (or translates) circuitembodiments 200, 210, 302, 216 into a netlist 730, where netlist 730 is,for example, a list of wires, transistors, logic gates, controlcircuits, I/O, models, etc., and describes the connections to otherelements and circuits in an integrated circuit design and recorded on atleast one of a machine readable medium. This may be an iterative processin which netlist 730 is resynthesized one or more times depending ondesign specifications and parameters for the circuit.

Design process 720 includes using a variety of inputs; for example,inputs from library elements 735 which may house a set of commonly usedelements, circuits, and devices, including models, layouts, and symbolicrepresentations, for a given manufacturing technology (e.g., differenttechnology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 740,characterization data 750, verification data 760, design rules 770, andtest data files 580, which may include test patterns and other testinginformation. Design process 720 further includes, for example, standardcircuit design processes such as timing analysis, verification tools,design rule checkers, place and route tools, etc. One of ordinary skillin the art of integrated circuit design can appreciate the extent ofpossible electronic design automation tools and applications used indesign process 720 without deviating from the scope and spirit of theinvention. The design structure of the invention embodiments is notlimited to any specific design flow.

Design process 720 preferably translates embodiments of the invention asshown in FIGS. 2-5, along with any additional integrated circuit designor data (if applicable), into a second design structure 790. Seconddesign structure 790 resides on a storage medium in a data format usedfor the exchange of layout data of integrated circuits (e.g. informationstored in a GDSII (GDS2), GL1, OASIS, or any other suitable format forstoring such design structures). Second design structure 790 maycomprise information such as, for example, test data files, designcontent files, manufacturing data, layout parameters, wires, levels ofmetal, vias, shapes, data for routing through the manufacturing line,and any other data required by a semiconductor manufacturer to produceembodiments of the invention as shown in FIGS. 2-5. Second designstructure 790 may then proceed to a stage 795 where, for example, seconddesign structure 790: proceeds to tape-out, is released tomanufacturing, is released to a mask house, is sent to another designhouse, is sent back to the customer, etc.

While the invention has been described with reference to a preferredembodiment or embodiments, it will be understood by those skilled in theart that various changes may be made and equivalents may be substitutedfor elements thereof without departing from the scope of the invention.In addition, many modifications may be made to adapt a particularsituation or material to the teachings of the invention withoutdeparting from the essential scope thereof. Therefore, it is intendedthat the invention not be limited to the particular embodiment disclosedas the best mode contemplated for carrying out this invention, but thatthe invention will include all embodiments falling within the scope ofthe appended claims.

1. A design structure embodied in a machine readable medium used in adesign process, the design structure comprising: a current controlled,phase locked loop device, including a phase detector configured tocompare a reference frequency to an output frequency of a currentcontrolled oscillator (ICO), said ICO further comprising a firstlatch-based delay stage having outputs connected to inputs of a secondlatch-based delay stage, and outputs of said second delay stage coupledback to inputs of said first delay stage; a charge pump coupled to saidphase detector and a low pass filter coupled to said charge pump; avoltage to current (V to I) converter coupled to said low pass filter,said V to I converter providing an output current for integral controlof said ICO; and a control circuit coupled to said ICO, said controlcircuit receiving increment and decrement outputs of said phasedetector, wherein said control circuit is configured to provideproportional control of said ICO through an amount of bias currentapplied to said ICO, said bias current based on the value of saidincrement and decrement outputs of said phase detector.
 2. The designstructure of claim 1, wherein said control circuit generates first andsecond output bias voltages used to determine the amount of bias currentutilized by said first and second latch-based delay stages, said firstand second output bias voltages being a function of said integralcontrol output current of said V to I converter.
 3. The design structureof claim 2, wherein said first and second output bias voltages of saidcontrol circuit are also a function of said increment and decrementoutputs of said phase detector, thereby providing proportional controlof said ICO.
 4. The design structure of claim 3, further comprising abias generator configured to provide current reference signals for saidcontrol circuit, said current reference signals determining the extentto which said increment and decrement outputs of said phase detectorprovide proportional control of said output frequency.
 5. The designstructure of claim 1, wherein said ICO is configured for gain controlthereof.
 6. The design structure of claim 5, wherein said gain controlis implemented through a gain control signal configured to adjust theresistance of cross-coupled paths within said first and second delaystages.
 7. The design structure of claim 1, wherein said low pass filtercomprises a capacitive, integral control element only.
 8. The designstructure of claim 1, wherein the design structure comprises a netlistdescribing the current controlled, phase locked loop device.
 9. Thedesign structure of claim 1, wherein the design structure resides onstorage medium as a data format used for the exchange of layout data ofintegrated circuits.
 10. The design structure of claim 1, wherein thedesign structure includes at least one of test data files,characterization data, verification data, programming data, or designspecifications.